1. Field of the Invention
The present invention relates to a semiconductor device which is prevented from having variation in a capacitance value and deterioration of breakdown voltage characteristics, and a method of manufacturing the same.
2. Description of the Related Art
A manufacturing method described below has been known as an example of a conventional method of manufacturing a semiconductor device. FIGS. 6A and 6B are cross-sectional views for explaining the conventional method of manufacturing a semiconductor device.
As shown in FIG. 6A, an N type epitaxial layer 52 is firstly formed on a P type semiconductor substrate 51. The epitaxial layer 52 is sectioned into multiple element formation regions by isolation regions 53. An NPN transistor 54 is formed in one of the element formation regions, and a capacitive element 55 is formed on a LOCOS oxide film in another element formation region. Then, diffusion layers of the NPN transistor 54 are formed, and a lower electrode 56 of the capacitive element 55 and a silicon nitride film 57 serving as a dielectric film are formed. Thereafter, an insulating layer 58 is formed above the epitaxial layer 52. Next, in the formation region of the capacitive element 55, an opening region 59 is formed in the insulating layer 58 to expose the silicon nitride film 57 therethrough for the purpose of forming an upper electrode.
Photoresist 60 is then formed above the epitaxial layer 52. Opening regions are formed in the photoresist 60 to form electrodes of the NPN transistor 54 and a lower extraction electrode of the capacitive element 55. Then, contact holes are formed in the silicon nitride film 57 and the insulating layer 58 by etching while using the photoresist 60 as a mask.
Next, as shown in FIG. 6B, the photoresist 60 (see FIG. 6A) is peeled off by ashing, and the top face of the insulating layer 58 and the like are cleaned by using, for example, sulfuric acid. Then, the electrodes of the NPN transistor 54 and the lower extraction electrode and an upper electrode 61 of the capacitive element 55 are formed in the contact holes and the opening region 59 formed in the insulating layer 58, respectively. (This technology is described for instance in Japanese Patent Application Publication No. Hei 5-90492 (pages 3 and 4, FIGS. 4 to 7).)